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ICCD
2001
IEEE
124views Hardware» more  ICCD 2001»
15 years 6 months ago
High-Level Power Modeling of CPLDs and FPGAs
In this paper, we present a high-level power modeling technique to estimate the power consumption of reconfigurable devices such as complex programmable logic devices (CPLDs) and ...
Li Shang, Niraj K. Jha
FPGA
2005
ACM
90views FPGA» more  FPGA 2005»
15 years 3 months ago
Using bus-based connections to improve field-programmable gate array density for implementing datapath circuits
Abstract—As the logic capacity of field-programmable gate arrays (FPGAs) increases, they are increasingly being used to implement large arithmetic-intensive applications, which ...
Andy Gean Ye, Jonathan Rose
DATE
2010
IEEE
180views Hardware» more  DATE 2010»
15 years 2 months ago
Reliability- and process variation-aware placement for FPGAs
Abstract—Negative bias temperature instability (NBTI) significantly affects nanoscale integrated circuit performance and reliability. The degradation in threshold voltage (Vth) d...
Assem A. M. Bsoul, Naraig Manjikian, Li Shang
FPGA
2004
ACM
116views FPGA» more  FPGA 2004»
15 years 3 months ago
Low-power technology mapping for FPGA architectures with dual supply voltages
In this paper we study the technology mapping problem of FPGA architectures with dual supply voltages (Vdds) for power optimization. This is done with the guarantee that the mappi...
Deming Chen, Jason Cong, Fei Li, Lei He