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TVLSI
2008
92views more  TVLSI 2008»
15 years 4 months ago
Reconfigurable Architecture for Network Flow Analysis
This paper describes a reconfigurable architecture based on field-programmable gate-array (FPGA) technology for monitoring and analyzing network traffic at increasingly high networ...
Sherif Yusuf, Wayne Luk, Morris Sloman, Naranker D...
TVLSI
2008
90views more  TVLSI 2008»
15 years 4 months ago
A Special-Purpose Architecture for Solving the Breakpoint Median Problem
Abstract--In this paper, we describe the design for a co-processor for whole-genome phylogenetic reconstruction. Our current design performs a parallelized breakpoint median comput...
Jason D. Bakos, Panormitis E. Elenis
CAI
2004
Springer
15 years 4 months ago
An Evolvable Combinational Unit for FPGAs
A complete hardware implementation of an evolvable combinational unit for FPGAs is presented. The proposed combinational unit consisting of a virtual reconfigurable circuit and evo...
Lukás Sekanina, Stepan Friedl
DCC
2010
IEEE
15 years 2 months ago
Neural Markovian Predictive Compression: An Algorithm for Online Lossless Data Compression
This work proposes a novel practical and general-purpose lossless compression algorithm named Neural Markovian Predictive Compression (NMPC), based on a novel combination of Bayesi...
Erez Shermer, Mireille Avigal, Dana Shapira
JUCS
2010
143views more  JUCS 2010»
15 years 2 months ago
Design of Arbiters and Allocators Based on Multi-Terminal BDDs
: Assigning one (more) shared resource(s) to several requesters is a function of arbiters (allocators). This class of decision-making modules can be implemented in a number of ways...
Václav Dvorák, Petr Mikusek