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FCCM
2006
IEEE
125views VLSI» more  FCCM 2006»
15 years 10 months ago
A Multithreaded Soft Processor for SoPC Area Reduction
The growth in size and performance of Field Programmable Gate Arrays (FPGAs) has compelled System-on-aProgrammable-Chip (SoPC) designers to use soft processors for controlling sys...
Blair Fort, Davor Capalija, Zvonko G. Vranesic, St...
RTSS
2006
IEEE
15 years 10 months ago
MCGREP - A Predictable Architecture for Embedded Real-Time Systems
Real-time systems design involves many important choices, including that of the processor. The fastest processors achieve performance by utilizing architectural features that make...
Jack Whitham, Neil C. Audsley
IOLTS
2005
IEEE
125views Hardware» more  IOLTS 2005»
15 years 9 months ago
Design of a Self Checking Reed Solomon Encoder
— In this paper, an innovative self-checking Reed Solomon encoder architecture is described. The presented architecture exploits some properties of the arithmetic operations in G...
Gian-Carlo Cardarilli, Salvatore Pontarelli, Marco...
FPL
2004
Springer
110views Hardware» more  FPL 2004»
15 years 9 months ago
Versatile Imaging Architecture Based on a System on Chip
Abstract. In this paper, a novel architecture dedicated to image processing is presented. The most original aspect of the approach is the use of a System On Chip implemented in a F...
Pierre Chalimbaud, François Berry
FPL
2004
Springer
171views Hardware» more  FPL 2004»
15 years 9 months ago
A Modular System for FPGA-Based TCP Flow Processing in High-Speed Networks
Field Programmable Gate Arrays (FPGAs) can be used in Intrusion Prevention Systems (IPS) to inspect application data contained within network flows. An IPS operating on high-speed...
David V. Schuehler, John W. Lockwood