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EH
1999
IEEE
351views Hardware» more  EH 1999»
15 years 8 months ago
Evolvable Hardware or Learning Hardware? Induction of State Machines from Temporal Logic Constraints
Here we advocate an approach to learning hardware based on induction of finite state machines from temporal logic constraints. The method involves training on examples, constraint...
Marek A. Perkowski, Alan Mishchenko, Anatoli N. Ch...
GLVLSI
2009
IEEE
170views VLSI» more  GLVLSI 2009»
15 years 8 months ago
Physical unclonable function and true random number generator: a compact and scalable implementation
Physical Unclonable Functions (PUF) and True Random Number Generators (TRNG) are two very useful components in secure system design. PUFs can be used to extract chip-unique signat...
Abhranil Maiti, Raghunandan Nagesh, Anand Reddy, P...
136
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CODES
2009
IEEE
15 years 8 months ago
Minimization of the reconfiguration latency for the mapping of applications on FPGA-based systems
Field-Programmable Gate Arrays (FPGAs) have become promising mapping fabric for the implementation of System-on-Chip (SoC) platforms, due to their large capacity and their enhance...
Vincenzo Rana, Srinivasan Murali, David Atienza, M...
CHES
2008
Springer
134views Cryptology» more  CHES 2008»
15 years 6 months ago
Ultra High Performance ECC over NIST Primes on Commercial FPGAs
Elliptic Curve Cryptosystems (ECC) have gained increasing acceptance in practice due to their significantly smaller bit size of the operands compared to other public-key cryptosyst...
Tim Güneysu, Christof Paar
CSREAESA
2006
15 years 5 months ago
Design and Implementation of SoPC with Multi-Bus on a Chip
SoPC (System on a Programmable Chip) is one important kind of SoC solution based on PLD (Programmable Logic Device). At the same time, PBD (Platform-based Design) has become popul...
Fangjun Jian, Jizhong Han, Chengde Han, Qin Zhang,...