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FPL
2009
Springer
145views Hardware» more  FPL 2009»
15 years 2 months ago
Area estimation and optimisation of FPGA routing fabrics
This paper presents a methodology for estimating and optimising FPGA routing fabrics using high-level modelling and convex optimisation techniques. Experimental methods for explor...
Alastair M. Smith, George A. Constantinides, Peter...
FPL
2004
Springer
143views Hardware» more  FPL 2004»
15 years 1 months ago
Exploring Area/Delay Tradeoffs in an AES FPGA Implementation
Abstract. Field-Programmable Gate Arrays (FPGAs) have lately become a popular target for implementing cryptographic block ciphers, as a well-designed FPGA solution can combine some...
Joseph Zambreno, David Nguyen, Alok N. Choudhary
82
Voted
MAM
2008
138views more  MAM 2008»
14 years 9 months ago
FPGA based tester tool for hybrid real-time systems
This paper presents a design methodology for a hybrid Hardwarein-the-Loop (HIL) tester tool, based on both discrete event system theory, given by timed automata, and continuous sy...
Jan Krakora, Zdenek Hanzálek
VLSISP
2002
199views more  VLSISP 2002»
14 years 9 months ago
Evaluation of CORDIC Algorithms for FPGA Design
Abstract. This paper presents a study of the suitability for FPGA design of full custom based CORDIC implementations. Since all these methods are based on redundant arithmetic, the...
Javier Valls, Martin Kuhlmann, Keshab K. Parhi
89
Voted
FPGA
2012
ACM
285views FPGA» more  FPGA 2012»
13 years 5 months ago
Optimizing SDRAM bandwidth for custom FPGA loop accelerators
Memory bandwidth is critical to achieving high performance in many FPGA applications. The bandwidth of SDRAM memories is, however, highly dependent upon the order in which address...
Samuel Bayliss, George A. Constantinides