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DATE
2006
IEEE
110views Hardware» more  DATE 2006»
15 years 3 months ago
Configurable multiprocessor platform with RTOS for distributed execution of UML 2.0 designed applications
This paper presents the design and full prototype implementation of a configurable multiprocessor platform that supports distributed execution of applications described in UML 2.0...
Tero Arpinen, Petri Kukkala, Erno Salminen, Marko ...
FCCM
2006
IEEE
100views VLSI» more  FCCM 2006»
15 years 3 months ago
Enabling a Uniform Programming Model Across the Software/Hardware Boundary
In this paper, we present hthreads, a unifying programming model for specifying application threads running within a hybrid CPU/FPGA system. Threads are specified from a single p...
Erik Anderson, Jason Agron, Wesley Peck, Jim Steve...
GLVLSI
2006
IEEE
90views VLSI» more  GLVLSI 2006»
15 years 3 months ago
Low-power clustering with minimum logic replication for coarse-grained, antifuse based FPGAs
This paper presents a minimum area, low-power driven clustering algorithm for coarse-grained, antifuse-based FPGAs under delay constraints. The algorithm accurately predicts logic...
Chang Woo Kang, Massoud Pedram
HICSS
2006
IEEE
131views Biometrics» more  HICSS 2006»
15 years 3 months ago
Design and Characterization of a Hardware Encryption Management Unit for Secure Computing Platforms
— Software protection is increasingly necessary for uses in commercial systems, digital content distributors, and military systems. The Secure Software (SecSoft) architecture is ...
Anthony J. Mahar, Peter M. Athanas, Stephen D. Cra...
ICRA
2006
IEEE
131views Robotics» more  ICRA 2006»
15 years 3 months ago
CMOS+FPGA Vision System for Visual Feedback of Mechanical Systems
— This paper describes a 1,000Hz visual feedback using the CMOS+FPGA vision. It is required to obtain positional and angular signals around 1,000Hz to control a mechanical system...
Kazuhiro Shimizu, Shinichi Hirai