Sciweavers

1862 search results - page 358 / 373
» FPGA
Sort
View
ICCAD
2006
IEEE
141views Hardware» more  ICCAD 2006»
15 years 6 months ago
A code refinement methodology for performance-improved synthesis from C
Although many recent advances have been made in hardware synthesis techniques from software programming languages such as C, the performance of synthesized hardware commonly suffe...
Greg Stitt, Frank Vahid, Walid A. Najjar
ICCAD
2002
IEEE
227views Hardware» more  ICCAD 2002»
15 years 6 months ago
Generic ILP versus specialized 0-1 ILP: an update
Optimized solvers for the Boolean Satisfiability (SAT) problem have many applications in areas such as hardware and software verification, FPGA routing, planning, etc. Further use...
Fadi A. Aloul, Arathi Ramani, Igor L. Markov, Kare...
80
Voted
ARITH
2009
IEEE
15 years 4 months ago
A Dual-Purpose Real/Complex Logarithmic Number System ALU
—The real Logarithmic Number System (LNS) allows fast and inexpensive multiplication and division but more expensive addition and subtraction as precision increases. Recent advan...
Mark G. Arnold, Sylvain Collange
80
Voted
DATE
2009
IEEE
119views Hardware» more  DATE 2009»
15 years 4 months ago
Bitstream relocation with local clock domains for partially reconfigurable FPGAs
—Partial Reconfiguration (PR) of FPGAs presents many opportunities for application design flexibility, enabling tasks to dynamically swap in and out of the FPGA without entire sy...
Adam Flynn, Ann Gordon-Ross, Alan D. George
DATE
2009
IEEE
159views Hardware» more  DATE 2009»
15 years 4 months ago
Design and implementation of a database filter for BLAST acceleration
— BLAST is a very popular Computational Biology algorithm. Since it is computationally expensive it is a natural target for acceleration research, and many reconfigurable archite...
Panagiotis Afratis, Constantinos Galanakis, Euripi...