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CDES
2006
158views Hardware» more  CDES 2006»
14 years 11 months ago
A Double Precision Floating Point Multiplier Suitably Designed for FPGAs and ASICs
In this paper, a double precision IEEE 754 floating-point multiplier with high speed and low power is presented. The bottleneck of any double precision floatingpoint multiplier des...
Himanshu Thapliyal, Vishal Verma, Hamid R. Arabnia
ERSA
2003
137views Hardware» more  ERSA 2003»
14 years 11 months ago
Next Generation Architecture for Heterogeneous Embedded Systems
The Software Communications Architecture (SCA), a mandatory specification for Software Radio implementations by the Joint Tactical Radio System (JTRS), defines a Common Object R...
S. Murat Bicer, Frank Pilhofer, Graham Bardouleau,...
CONEXT
2009
ACM
14 years 10 months ago
SafeGuard: safe forwarding during route changes
This paper presents the design and evaluation of SafeGuard, an intra-domain routing system that can safely forward packets to their destinations even when routes are changing. Saf...
Ang Li, Xiaowei Yang, David Wetherall
DSD
2010
IEEE
190views Hardware» more  DSD 2010»
14 years 9 months ago
Hardware-Based Speed Up of Face Recognition Towards Real-Time Performance
— Real-time face recognition by computer systems is required in many commercial and security applications because it is the only way to protect privacy and security in the sea of...
I. Sajid, Sotirios G. Ziavras, M. M. Ahmed
SIGCOMM
2010
ACM
14 years 9 months ago
SourceSync: a distributed wireless architecture for exploiting sender diversity
Diversity is an intrinsic property of wireless networks. Recent years have witnessed the emergence of many distributed protocols like ExOR, MORE, SOAR, SOFT, and MIXIT that exploi...
Hariharan Rahul, Haitham Hassanieh, Dina Katabi