Sciweavers

1862 search results - page 40 / 373
» FPGA
Sort
View
FPGA
1999
ACM
155views FPGA» more  FPGA 1999»
15 years 2 months ago
FPGA Routing Architecture: Segmentation and Buffering to Optimize Speed and Density
In this work we investigate the routing architecture of FPGAs, focusing primarily on determining the best distribution of routing segment lengths and the best mix of pass transist...
Vaughn Betz, Jonathan Rose
FPGA
2000
ACM
175views FPGA» more  FPGA 2000»
15 years 1 months ago
An FPGA implementation and performance evaluation of the Serpent block cipher
With the expiration of the Data Encryption Standard (DES) in 1998, the Advanced Encryption Standard (AES) development process is well underway. It is hoped that the result of the ...
Adam J. Elbirt, Christof Paar
ICCAD
2007
IEEE
157views Hardware» more  ICCAD 2007»
15 years 6 months ago
Performance and power evaluation of a 3D CMOS/nanomaterial reconfigurable architecture
—In this paper, we introduce a novel reconfigurable architecture, named 3D nFPGA, which utilizes 3D integration techniques and new nanoscale materials synergistically. The propos...
Chen Dong, Deming Chen, Sansiri Tanachutiwat, Wei ...
FPGA
2007
ACM
142views FPGA» more  FPGA 2007»
15 years 3 months ago
Parametric yield in FPGAs due to within-die delay variations: a quantitative analysis
Variations in the semiconductor fabrication process results in variability in parameters between transistors on the same die, a problem exacerbated by lithographic scaling. The re...
N. Pete Sedcole, Peter Y. K. Cheung
DATE
2006
IEEE
151views Hardware» more  DATE 2006»
15 years 3 months ago
40Gbps de-layered silicon protocol engine for TCP record
We present a de-layered protocol engine for termination of 40Gbps TCP connections using a reconfigurable FPGA silicon platform. This protocol engine is designed for a planned att...
H. Shrikumar