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CCECE
2006
IEEE
15 years 3 months ago
Hardware Edge Detection using an Altera Stratix NIOS2 Development Kit
— Edge detection is a computer vision algorithm that is very processor intensive. It is possible to increase the speed of the algorithm by using hardware parallelism. This paper ...
Jay Kraut
DATE
2006
IEEE
94views Hardware» more  DATE 2006»
15 years 3 months ago
An analytical state dependent leakage power model for FPGAs
In this paper we present a state dependent analytical leakage power model for FPGAs. The model accounts for subthreshold leakage and gate leakage in FPGAs, since these are the two...
Akhilesh Kumar, Mohab Anis
DSD
2006
IEEE
116views Hardware» more  DSD 2006»
15 years 3 months ago
Hardware/Software Co-design Applied to Reed-Solomon Decoding for the DMB Standard
This paper addresses the implementation of ReedSolomon decoding for battery-powered wireless devices. The scope of this paper is constrained by the Digital Media Broadcasting (DMB...
Arjan C. Dam, Michel G. J. Lammertink, Kenneth C. ...
ISCAS
2005
IEEE
131views Hardware» more  ISCAS 2005»
15 years 3 months ago
A low-complexity scanned-array 3D IIR frequency-planar filter
— We extend a 3D differential-operator-based filter architecture to a 3D IIR FPGA filter circuit implementation employing a recently proposed scanned-array method, which uses a s...
Arjuna Madanayake, Leonard T. Bruton
FPGA
2004
ACM
133views FPGA» more  FPGA 2004»
15 years 3 months ago
FPGAs vs. CPUs: trends in peak floating-point performance
Moore’s Law states that the number of transistors on a device doubles every two years; however, it is often (mis)quoted based on its impact on CPU performance. This important co...
Keith D. Underwood