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FPGA
2010
ACM
191views FPGA» more  FPGA 2010»
15 years 4 months ago
Voter insertion algorithms for FPGA designs using triple modular redundancy
Triple Modular Redundancy (TMR) is a common reliability technique for mitigating single event upsets (SEUs) in FPGA designs operating in radiation environments. For FPGA systems t...
Jonathan M. Johnson, Michael J. Wirthlin
FPGA
2007
ACM
185views FPGA» more  FPGA 2007»
15 years 3 months ago
Power-aware FPGA logic synthesis using binary decision diagrams
Power consumption in field programmable gate arrays (FPGAs) has become an important issue as the FPGA market has grown to include mobile platforms. In this work we present a power...
Kevin Oo Tinmaung, David Howland, Russell Tessier
FCCM
2006
IEEE
144views VLSI» more  FCCM 2006»
15 years 3 months ago
Combining Instruction Coding and Scheduling to Optimize Energy in System-on-FPGA
In this paper, we investigate a combination of two techniques — instruction coding and instruction re-ordering — for optimizing energy in embedded processor control. We presen...
Robert G. Dimond, Oskar Mencer, Wayne Luk
ISCAS
2005
IEEE
154views Hardware» more  ISCAS 2005»
15 years 3 months ago
HIBI-based multiprocessor SoC on FPGA
Abstract — FPGAs offer excellent platform for System-onChips consisting of Intellectual Property (IP) blocks. The problem is that IP blocks and their interconnections are often F...
Erno Salminen, Ari Kulmala, Timo D. Hämä...
ISLPED
2003
ACM
155views Hardware» more  ISLPED 2003»
15 years 3 months ago
Low-power high-level synthesis for FPGA architectures
This paper addresses two aspects of low-power design for FPGA circuits. First, we present an RT-level power estimator for FPGAs with consideration of wire length. The power estima...
Deming Chen, Jason Cong, Yiping Fan