Sciweavers

1862 search results - page 60 / 373
» FPGA
Sort
View
AHS
2006
IEEE
133views Hardware» more  AHS 2006»
15 years 3 months ago
Gate-level Morphogenetic Evolvable Hardware for Scalability and Adaptation on FPGAs
Traditional approaches to evolvable hardware (EHW), in which the field programmable gate array (FPGA) configuration is directly encoded, have not scaled well with increasing cir...
Justin Lee, Joaquin Sitte
SLIP
2006
ACM
15 years 3 months ago
The routability of multiprocessor network topologies in FPGAs
A fundamental difference between ASICs and FPGAs is that wires in ASICs are designed such that it matches the requirements of a particular design. Wire parameters such as: length...
Manuel Saldaña, Lesley Shannon, Paul Chow
MSE
2005
IEEE
154views Hardware» more  MSE 2005»
15 years 3 months ago
A Platform FPGA-Based Hardware-Software Undergraduate Laboratory
Almost all universities offer introductory courses that focus on microcontroller-based systems and embedded programming. Advanced course offerings vary, and are often not availabl...
Joseph Schneider, Mikel Bezdek, Ziyu Zhang, Zhao Z...
FPGA
2005
ACM
105views FPGA» more  FPGA 2005»
15 years 3 months ago
Soft error rate estimation and mitigation for SRAM-based FPGAs
FPGA-based designs are more susceptible to single-event upsets (SEUs) compared to ASIC designs. Soft error rate (SER) estimation is a crucial step in the design of soft error tole...
Ghazanfar Asadi, Mehdi Baradaran Tahoori
FPGA
2005
ACM
80views FPGA» more  FPGA 2005»
15 years 3 months ago
Simultaneous timing-driven placement and duplication
Logic duplication is an effective method for improving circuit performance. In this paper we present an algorithm named SPD that performs simultaneous placement and duplication to...
Gang Chen, Jason Cong