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CHES
2003
Springer
247views Cryptology» more  CHES 2003»
15 years 3 months ago
Very Compact FPGA Implementation of the AES Algorithm
Abstract. In this paper a compact FPGA architecture for the AES algorithm with 128-bit key targeted for low-cost embedded applications is presented. Encryption, decryption and key ...
Pawel Chodowiec, Kris Gaj
DELTA
2010
IEEE
15 years 2 months ago
Algorithm Transformation for FPGA Implementation
— High level hardware description languages aim to make hardware design more like programming software. These languages are often used to accelerate legacy software algorithms by ...
Donald G. Bailey, Christopher T. Johnston
ARC
2006
Springer
85views Hardware» more  ARC 2006»
15 years 1 months ago
Time-Memory Trade-Off Attack on FPGA Platforms: UNIX Password Cracking
Abstract. This paper presents a hardware architecture for UNIX password cracking using Hellman's time-memory trade-off; it is the first hardware design for a key search machin...
Nele Mentens, Lejla Batina, Bart Preneel, Ingrid V...
DAC
1995
ACM
15 years 1 months ago
New Performance-Driven FPGA Routing Algorithms
—Motivated by the goal of increasing the performance of FPGA-based designs, we propose new Steiner and arborescence FPGA routing algorithms. Our Steiner tree constructions signiï...
Michael J. Alexander, Gabriel Robins
FPL
2008
Springer
112views Hardware» more  FPL 2008»
14 years 11 months ago
Secure FPGA configuration architecture preventing system downgrade
In the context of FPGAs, system downgrade consists in preventing the update of the hardware configuration or in replaying an old bitstream. The objective can be to preclude a syst...
Benoît Badrignans, Reouven Elbaz, Lionel Tor...