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ET
2006
154views more  ET 2006»
14 years 9 months ago
An Automated BIST Architecture for Testing and Diagnosing FPGA Interconnect Faults
We present an efficient built-in self-test (BIST) architecture for testing and diagnosing stuck-at faults, delay faults, and bridging faults in FPGA interconnect resources. The BIS...
Jack Smith, Tian Xia, Charles E. Stroud
CEE
2007
105views more  CEE 2007»
14 years 9 months ago
Compact modular exponentiation accelerator for modern FPGA devices
We present a compact FPGA implementation of a modular exponentiation accelerator suited for cryptographic applications. The implementation efficiently exploits the properties of m...
Timo Alho, Panu Hämäläinen, Marko H...
FTEDA
2007
156views more  FTEDA 2007»
14 years 9 months ago
FPGA Architecture: Survey and Challenges
Field-Programmable Gate Arrays (FPGAs) have become one of the key digital circuit implementation media over the last decade. A crucial part of their creation lies in their archite...
Ian Kuon, Russell Tessier, Jonathan Rose
ERSA
2010
159views Hardware» more  ERSA 2010»
14 years 7 months ago
Acceleration of FPGA Fault Injection Through Multi-Bit Testing
SRAM-based FPGA devices are an attractive option for data processing on space-based platforms, due to high computational capabilities and a lower power envelope than traditional pr...
Grzegorz Cieslewski, Alan D. George, Adam Jacobs
DAC
2004
ACM
15 years 10 months ago
FPGA power reduction using configurable dual-Vdd
Power optimization is of growing importance for FPGAs in nanometer technologies. Considering dual-Vdd technique, we show that configurable power supply is required to obtain a sat...
Fei Li, Yan Lin, Lei He