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    ASPDAC
    2001
    ACM
    120views Hardware» more  ASPDAC 2001»
    Virtual Java/FPGA interface for networked reconfiguration
    15 years 1 months ago
    Virtual Java/FPGA interface for networked reconfiguration
    Download  www.cesca.centers.vt.edu
    Abstract- Avirtual interfacebetweenJava andFPGA for networked reconfigurationis presented. ThroughtheJavaflFPGAinterface,Java applicationscan exploithardwareaccelerators with FPGAs...
    Yajun Ha, Geert Vanmeerbeeck, Patrick Schaumont, S...
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    ASPDAC
    2005
    ACM
    89views Hardware» more  ASPDAC 2005»
    Routing track duplication with fine-grained power-gating for FPGA interconnect power reduction
    14 years 11 months ago
    Routing track duplication with fine-grained power-gating for FPGA interconnect power reduction
    Download  www.ee.ucla.edu
    Power has become an increasingly important design constraint for FPGAs in nanometer technologies, and global interconnects should be the focus of FPGA power reduction as they cons...
    Yan Lin, Fei Li, Lei He
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    FPGA
    2008
    ACM
    131views FPGA» more  FPGA 2008»
    WireMap: FPGA technology mapping for improved routability
    14 years 11 months ago
    WireMap: FPGA technology mapping for improved routability
    Download  www.eecs.berkeley.edu
    This paper presents a new technology mapper, WireMap. The mapper uses an edge flow heuristic to improve the routability of a mapped design. The heuristic is applied during the ite...
    Stephen Jang, Billy Chan, Kevin Chung, Alan Mishch...
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    FPGA
    2008
    ACM
    184views FPGA» more  FPGA 2008»
    Mapping for better than worst-case delays in LUT-based FPGA designs
    14 years 11 months ago
    Mapping for better than worst-case delays in LUT-based FPGA designs
    Download  cadlab.cs.ucla.edu
    Current advances in chip design and manufacturing have allowed IC manufacturing to approach the nanometer range. As the feature size scales down, greater variability is experience...
    Kirill Minkovich, Jason Cong
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    DT
    1998
    85views more  DT 1998»
    How Much Logic Should Go in an FPGA Logic Block?
    14 years 9 months ago
    How Much Logic Should Go in an FPGA Logic Block?
    Download  www.eecg.toronto.edu
    The logic blocks of most modern FPGAs contain clusters of look-up tables and flip flops, yet little is known about good choices for several key architectural parameters related ...
    Vaughn Betz, Jonathan Rose
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