1862 search results - page 80 / 373 » FPGA |
CHES
2007
Springer
15 years 4 months ago
2007
Springer
This paper describes a modular exponentiation processing method and circuit architecture that can exhibit the maximum performance of FPGA resources. The modular exponentiation arch...
DATE
2006
IEEE
15 years 3 months ago
2006
IEEE
In this paper the concept of a reconfigurable hardware macro to be used as a generic building block in lowpower, low-cost SoC for multioperable GNSS positioning is described, feat...
IPPS
2006
IEEE
15 years 3 months ago
2006
IEEE
The novel design of an efficient FPGA interconnection architecture with multiple Switch Boxes (SB) and hardwired connections for realizing data intensive applications (i.e. DSP ap...
GLVLSI
2005
IEEE
15 years 3 months ago
2005
IEEE
This paper addresses a pipelined partial rolling (PPR) architecture for the AES encryption. The key technique is the PPR architecture, which is suitable for FPGA implementation. U...
HAPTICS
2005
IEEE
15 years 3 months ago
2005
IEEE
Wearable haptics necessitates using low power, small, inexpensive tactors that are typically used as pager motors in cellular phones. One of their limitations is that it appears t...