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92
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FPL
2008
Springer
110views Hardware» more  FPL 2008»
15 years 5 months ago
Metawire: Using FPGA configuration circuitry to emulate a Network-on-Chip
While there have been many reported implementations of Networks-on-Chip (NoCs) on FPGAs, they have not seen the same acceptance as NoCs on ASICs. One reason is that communication ...
Matthew Shelburne, Cameron Patterson, Peter Athana...
137
Voted
ERSA
2006
133views Hardware» more  ERSA 2006»
15 years 5 months ago
An FPGA based Co-Design Architecture for MIMO Lattice Decoders
MIMO systems have attracted great attentions because of their huge capacity. The hardware implementation of MIMO decoder becomes a challenging task as the complexity of the MIMO sy...
Cao Liang, Jing Ma, Xin-Ming Huang
132
Voted
ERSA
2003
118views Hardware» more  ERSA 2003»
15 years 5 months ago
A Novel Multi-Speed, Power Saving Architecture for SiGe HBT FPGA
The availability of SiGe HBT devices has opened a door for Gigahertz FPGAs. However, the large device power consumption limits its scale. In order to solve this problem, a Multipl...
Jong-Ru Guo, Chao You, Michael Chu, Kuan Zhou, You...
142
Voted
IEICET
2008
124views more  IEICET 2008»
15 years 3 months ago
A Secure Content Delivery System Based on a Partially Reconfigurable FPGA
We developed a content delivery system using a partially reconfigurable FPGA to securely distribute digital content on the Internet. With partial reconfigurability of a Xilinx Vir...
Yohei Hori, Hiroyuki Yokoyama, Hirofumi Sakane, Ke...
124
Voted
FPL
2010
Springer
134views Hardware» more  FPL 2010»
15 years 1 months ago
GPU Versus FPGA for High Productivity Computing
Heterogeneous or co-processor architectures are becoming an important component of high productivity computing systems (HPCS). In this work the performance of a GPU based HPCS is c...
David Huw Jones, Adam Powell, Christos-Savvas Boug...