This paper discusses hardware development of a realtime H.264/AVC video decoder. Synthesis results are presented for example implementations of the inverse quantization, inverse t...
Low power techniques in a FPGA implementation of the hash function called Luffa are presented in this paper. This hash function is under consideration for adoption as standard. Tw...
Paris Kitsos, Nicolas Sklavos, Athanassios N. Skod...
FPGAs offer flexibility and cost-effectiveness that ASICs cannot match; however, their performance is quite poor in comparison, especially for arithmetic dominated circuits. To ad...
Philip Brisk, Ajay K. Verma, Paolo Ienne, Hadi Par...
In this paper, we study the problem of performance-driven multi-level circuit clustering with application to hierarchical FPGA designs. We first show that the performance-driven m...
This paper attempts to quantify the optimality of FPGA technology mapping algorithms. We develop an algorithm, based on Boolean satisfiability (SAT), that is able to map a small s...
Andrew C. Ling, Deshanand P. Singh, Stephen Dean B...