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105
Voted
ASAP
2006
IEEE
150views Hardware» more  ASAP 2006»
15 years 5 months ago
Architecture design of an H.264/AVC decoder for real-time FPGA implementation
This paper discusses hardware development of a realtime H.264/AVC video decoder. Synthesis results are presented for example implementations of the inverse quantization, inverse t...
Thomas Warsaw, Marcin Lukowiak
123
Voted
DSD
2010
IEEE
126views Hardware» more  DSD 2010»
15 years 3 months ago
Low Power FPGA Implementations of 256-bit Luffa Hash Function
Low power techniques in a FPGA implementation of the hash function called Luffa are presented in this paper. This hash function is under consideration for adoption as standard. Tw...
Paris Kitsos, Nicolas Sklavos, Athanassios N. Skod...
DAC
2007
ACM
16 years 4 months ago
Enhancing FPGA Performance for Arithmetic Circuits
FPGAs offer flexibility and cost-effectiveness that ASICs cannot match; however, their performance is quite poor in comparison, especially for arithmetic dominated circuits. To ad...
Philip Brisk, Ajay K. Verma, Paolo Ienne, Hadi Par...
DAC
2001
ACM
16 years 4 months ago
Performance-Driven Multi-Level Clustering with Application to Hierarchical FPGA Mapping
In this paper, we study the problem of performance-driven multi-level circuit clustering with application to hierarchical FPGA designs. We first show that the performance-driven m...
Jason Cong, Michail Romesis
DAC
2005
ACM
16 years 4 months ago
FPGA technology mapping: a study of optimality
This paper attempts to quantify the optimality of FPGA technology mapping algorithms. We develop an algorithm, based on Boolean satisfiability (SAT), that is able to map a small s...
Andrew C. Ling, Deshanand P. Singh, Stephen Dean B...