1243 search results - page 170 / 249 » FPZL Schedulability Analysis |
118
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DATE
1999
IEEE
15 years 4 months ago
1999
IEEE
In this paper, new and efficient BIST methodology and BIST hardware insertion algorithms are presented for RTL data paths obtained from high level synthesis. The methodology is ba...
105
Voted
IEEEPACT
1999
IEEE
15 years 4 months ago
1999
IEEE
Increases in instruction level parallelism are needed to exploit the potential parallelism available in future wide issue architectures. Predicated execution is an architectural m...
RSP
1999
IEEE
15 years 4 months ago
1999
IEEE
Though synchronous dataflow (SDF) graph has been a successful input specification language for digital signal processing (DSP) applications, lack of support for global states makes...
101
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ASAP
1997
IEEE
15 years 4 months ago
1997
IEEE
This paper presents a technique to map automatically a complete digital signal processing (DSP) application onto a parallel machine with distributed memory. Unlike other applicati...
124
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RANDOM
1998
Springer
15 years 4 months ago
1998
Springer
We are given a sequence of items that can be packed into m unit size bins. In the classical bin packing problem we x the size of the bins and try to pack the items in the minimum ...