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» Factoring large numbers with programmable hardware
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FPL
2004
Springer
93views Hardware» more  FPL 2004»
15 years 5 months ago
The Impact of Pipelining on Energy per Operation in Field-Programmable Gate Arrays
This paper investigates experimentally the quantitative impact of pipelining on energy per operation for two representative FPGA devices: a 0.13µm CMOS high density/high speed FPG...
Steven J. E. Wilton, Su-Shin Ang, Wayne Luk
ETFA
2008
IEEE
15 years 1 months ago
Hardware acceleration for verifiable, adaptive real-time communication
Distributed real-time applications implement distributed applications with timeliness requirements. Such systems require a deterministic communication medium with bounded communic...
Sebastian Fischmeister, Insup Lee, Robert Trausmut...
FPL
2006
Springer
127views Hardware» more  FPL 2006»
15 years 3 months ago
On-FPGA Communication Architectures and Design Factors
The recent development of Platform-FPGA or FieldProgrammable System-on-Chip architectures, with immersed coarse-grain processors, embedded memories and IP cores, offers the potent...
Terrence S. T. Mak, N. Pete Sedcole, Peter Y. K. C...
ET
2000
80views more  ET 2000»
14 years 11 months ago
A New Method for Testing Re-Programmable PLAs
: We present a method for obtaining a minimal set of test configurations and their associated set oftest patterns that completely tests re-programmable Programmable Logic Arrays (P...
Charles E. Stroud, James R. Bailey, Johan R. Emmer...
EGH
2007
Springer
15 years 5 months ago
Programmable shaders for deformation rendering
In this paper, we present a method for rendering deformations as part of the programmable shader pipeline of contemporary Graphical Processing Units. In our method, we allow gener...
Carlos D. Correa, Deborah Silver