317 search results - page 64 / 64 » Factoring logic functions using graph partitioning |
ASPLOS
2006
ACM
15 years 5 months ago
2006
ACM
Growing on-chip wire delays are motivating architectural features that expose on-chip communication to the compiler. EDGE architectures are one example of communication-exposed mi...
105
Voted
CORR
2008
Springer
14 years 11 months ago
2008
Springer
In this paper, we propose a general cross-layer optimization framework in which we explicitly consider both the heterogeneous and dynamically changing characteristics of delay-sens...