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ISQED
2006
IEEE
78views Hardware» more  ISQED 2006»
14 years 7 days ago
Simultaneous Statistical Delay and Slew Optimization for Interconnect Pipelines
Process variation has become a major concern in the design of many nanometer circuits, including interconnect pipelines. This paper develops closed-form models to predict the dela...
Andrew Havlir, David Z. Pan
NOCS
2008
IEEE
14 years 18 days ago
Network Simplicity for Latency Insensitive Cores
In this paper we examine a latency insensitive network composed of very fast and simple circuits that connects SoC cores that are also latency insensitive, de-synchronized, or asy...
Daniel Gebhardt, JunBok You, W. Scott Lee, Kenneth...
VLSID
2006
IEEE
150views VLSI» more  VLSID 2006»
14 years 6 months ago
A Comprehensive SoC Design Methodology for Nanometer Design Challenges
SoC design methodologies are under constant revision due to adoption of fast shrinking process technologies at nanometer levels. Nanometer process geometries exhibit new complex d...
R. Raghavendra Kumar, Ricky Bedi, Ramadas Rajagopa...