8 search results - page 2 / 2 » Fast Buffer Insertion for Yield Optimization Under Process V... |
ISQED
2006
IEEE
14 years 7 days ago
2006
IEEE
Process variation has become a major concern in the design of many nanometer circuits, including interconnect pipelines. This paper develops closed-form models to predict the dela...
NOCS
2008
IEEE
14 years 18 days ago
2008
IEEE
In this paper we examine a latency insensitive network composed of very fast and simple circuits that connects SoC cores that are also latency insensitive, de-synchronized, or asy...
VLSID
2006
IEEE
14 years 6 months ago
2006
IEEE
SoC design methodologies are under constant revision due to adoption of fast shrinking process technologies at nanometer levels. Nanometer process geometries exhibit new complex d...