Sciweavers

308 search results - page 12 / 62
» Fast Comparisons of Circuit Implementations
Sort
View
ISLPED
2006
ACM
140views Hardware» more  ISLPED 2006»
15 years 5 months ago
L-CBF: a low-power, fast counting bloom filter architecture
—An increasing number of architectural techniques rely on hardware counting bloom filters (CBFs) to improve upon the enegy, delay and complexity of various processor structures. ...
Elham Safi, Andreas Moshovos, Andreas G. Veneris
VLSID
2002
IEEE
135views VLSI» more  VLSID 2002»
16 years 4 days ago
An Efficient Algorithm for Low Power Pass Transistor Logic Synthesis
In this paper, we address the problem of power dissipation minimization in combinational circuits implemented using pass transistor logic (PTL). We transform the problem of power ...
Rupesh S. Shelar, Sachin S. Sapatnekar
FPL
2005
Springer
140views Hardware» more  FPL 2005»
15 years 5 months ago
A Configuration Memory Architecture for Fast Run-Time-Reconfiguration of FPGAs
This paper presents a configuration memory architecture that offers fast FPGA reconfiguration. The underlying principle behind the design is the use of fine-grained partial rec...
Usama Malik, Oliver Diessel
FPL
2009
Springer
99views Hardware» more  FPL 2009»
15 years 4 months ago
Exploiting fast carry-chains of FPGAs for designing compressor trees
Fast carry chains featuring dedicated adder circuitry is a distinctive feature of modern FPGAs. The carry chains bypass the general routing network and are embedded in the logic b...
Hadi Parandeh-Afshar, Philip Brisk, Paolo Ienne
HPDC
2012
IEEE
13 years 2 months ago
VNET/P: bridging the cloud and high performance computing through fast overlay networking
networking with a layer 2 abstraction provides a powerful model for virtualized wide-area distributed computing resources, including for high performance computing (HPC) on collec...
Lei Xia, Zheng Cui, John R. Lange, Yuan Tang, Pete...