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ICRA
2009
IEEE
144views Robotics» more  ICRA 2009»
15 years 6 months ago
Reusable electronics and adaptable communication as implemented in the odin modular robot
Abstract— This paper describes the electronics and communication system of Odin, a novel heterogeneous modular robot made of links and joints. The electronics is divided into two...
Ricardo Franco Mendoza Garcia, Andreas Lyder, Davi...
AHS
2007
IEEE
215views Hardware» more  AHS 2007»
14 years 12 months ago
Online Evolution for a High-Speed Image Recognition System Implemented On a Virtex-II Pro FPGA
Online incremental evolution for a complex high-speed pattern recognition architecture has been implemented on a Xilinx Virtex-II Pro FPGA. The fitness evaluation module is entir...
Kyrre Glette, Jim Torresen, Moritoshi Yasunaga
ASAP
2006
IEEE
111views Hardware» more  ASAP 2006»
15 years 5 months ago
Fast Bit Compression and Expansion with Parallel Extract and Parallel Deposit Instructions
Current microprocessor instruction set architectures are word oriented, with some subword support. Many important applications, however, can realize substantial performance benefi...
Yedidya Hilewitz, Ruby B. Lee
SODA
2003
ACM
131views Algorithms» more  SODA 2003»
15 years 1 months ago
Root comparison techniques applied to computing the additively weighted Voronoi diagram
This work examines algebraic techniques for comparing quadratic algebraic numbers, thus yielding methods for deciding key predicates in various geometric constructions. Our motiva...
Menelaos I. Karavelas, Ioannis Z. Emiris
ASPDAC
1999
ACM
113views Hardware» more  ASPDAC 1999»
15 years 4 months ago
An Efficient Iterative Improvement Technique for VLSI Circuit Partitioning Using Hybrid Bucket Structures
In this paper, we present a fast and efficient Iterative Improvement Partitioning (IIP) technique for VLSI circuits and hybrid bucket structures on its implementation. Due to thei...
C. K. Eem, J. W. Chong