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GLVLSI
2006
IEEE
185views VLSI» more  GLVLSI 2006»
15 years 5 months ago
Application of fast SOCP based statistical sizing in the microprocessor design flow
In this paper we have applied statistical sizing in an industrial setting. Efficient implementation of the statistical sizing algorithm is achieved by utilizing a dedicated interi...
Murari Mani, Mahesh Sharma, Michael Orshansky
ISQED
2003
IEEE
134views Hardware» more  ISQED 2003»
15 years 5 months ago
Concurrent Fault Detection in Random Combinational Logic
We discuss a non-intrusive methodology for concurrent fault detection in random combinational logic. The proposed method is similar to duplication, wherein a replica of the circui...
Petros Drineas, Yiorgos Makris
ISLPED
1995
ACM
122views Hardware» more  ISLPED 1995»
15 years 3 months ago
A multiple clocking scheme for low power RTL design
This paper presents an e ective multiple clocking scheme for lower power RTL circuit design. The basis is to partition a behavioral description of the circuit into m modules fed b...
Christos A. Papachristou, Mark Spining, Mehrdad No...
CODES
2005
IEEE
15 years 5 months ago
High-level synthesis for large bit-width multipliers on FPGAs: a case study
In this paper, we present the analysis, design and implementation of an estimator to realize large bit width unsigned integer multiplier units. Larger multiplier units are require...
Gang Quan, James P. Davis, Siddhaveerasharan Devar...
ICCD
2000
IEEE
87views Hardware» more  ICCD 2000»
15 years 4 months ago
Binary and Multi-Valued SPFD-Based Wire Removal in PLA Networks
This paper describes the application of binary and multivalued SPFD-based wire removal techniques for circuit implementations utilizing networks of PLAs. It has been shown that a ...
Subarnarekha Sinha, Sunil P. Khatri, Robert K. Bra...