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DAC
2007
ACM
16 years 25 days ago
IPR: An Integrated Placement and Routing Algorithm
Abstract-- In nanometer-scale VLSI technologies, several interconnect issues like routing congestion and interconnect delay have become the main concerns in placement. However, all...
Min Pan, Chris C. N. Chu
ARITH
2001
IEEE
15 years 3 months ago
Computer Arithmetic-A Processor Architect's Perspective
The Instruction Set Architecture (ISA) of a programmable processor is the native languageof the machine. It defines the set of operations and resourcesthat are optimized for that ...
Ruby B. Lee
IDEAS
2007
IEEE
135views Database» more  IDEAS 2007»
15 years 6 months ago
Bitmap Index Design Choices and Their Performance Implications
Historically, bitmap indexing has provided an important database capability to accelerate queries. However, only a few database systems have implemented these indexes because of t...
Elizabeth J. O'Neil, Patrick E. O'Neil, Kesheng Wu
VLSID
2004
IEEE
139views VLSI» more  VLSID 2004»
16 years 6 days ago
Open Defects Detection within 6T SRAM Cells using a No Write Recovery Test Mode
The detection of all open defects within 6T SRAM cells is always a challenge due to the significant test time requirements. This paper proposes a new design-for-test (DFT) techniq...
André Ivanov, Baosheng Wang, Josh Yang
VLSID
2003
IEEE
82views VLSI» more  VLSID 2003»
16 years 6 days ago
SPaRe: Selective Partial Replication for Concurrent Fault Detection in FSMs
We propose a non-intrusive methodology for concurrent fault detection in FSMs. The proposed method is similar to duplication, wherein a replica of the circuit acts as a predictor ...
Petros Drineas, Yiorgos Makris