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ICCAD
2006
IEEE
183views Hardware» more  ICCAD 2006»
15 years 8 months ago
Soft error derating computation in sequential circuits
Soft error tolerant design becomes more crucial due to exponential increase in the vulnerability of computer systems to soft errors. Accurate estimation of soft error rate (SER), ...
Hossein Asadi, Mehdi Baradaran Tahoori
ICCAD
2003
IEEE
161views Hardware» more  ICCAD 2003»
15 years 8 months ago
A General S-Domain Hierarchical Network Reduction Algorithm
This paper presents an efficient method to reduce complexities of a linear network in s-domain. The new method works on circuit matrices directly and reduces the circuit complexi...
Sheldon X.-D. Tan
PATMOS
2004
Springer
15 years 5 months ago
Investigation of Low-Power Low-Voltage Circuit Techniques for a Hybrid Full-Adder Cell
A full-adder implemented by combining branch-based logic and pass-gate logic is presented in this contribution. A comparison between this proposed full-adder (named BBL PT) and its...
Ilham Hassoune, Amaury Nève, Jean-Didier Le...
FPL
2009
Springer
166views Hardware» more  FPL 2009»
15 years 4 months ago
Modeling post-techmapping and post-clustering FPGA circuit depth
This paper presents an analytical model that relates FPGA architectural parameters to the expected speed of FPGA implementation. More precisely, the model relates the lookuptable ...
Joydip Das, Steven J. E. Wilton, Philip Heng Wai L...
EVOW
2000
Springer
15 years 3 months ago
Prediction of Power Requirements for High-Speed Circuits
Modern VLSI design methodologies and manufacturing technologies are making circuits increasingly fast. The quest for higher circuit performance and integration density stems from f...
Fulvio Corno, Maurizio Rebaudengo, Matteo Sonza Re...