308 search results - page 9 / 62 » Fast Comparisons of Circuit Implementations |
ISLPED
1996
ACM
15 years 3 months ago
1996
ACM
This paper examines the energy delay implications of partial product reduction methods employed in parallel multiplier implementations. Radix 4 Modified Booth Algorithm (MBA) is c...
DATE
2008
IEEE
15 years 6 months ago
2008
IEEE
Comparator-based switched capacitor (CBSC) circuits present an alternative approach to designing sampled data systems based on the principle of detecting a virtual ground conditio...
FPL
2009
Springer
15 years 4 months ago
2009
Springer
Automated code generation and performance tuning techniques for concurrent architectures such as GPUs, Cell and FPGAs can provide integer factor speedups over multi-core processor...
HPN
1994
15 years 1 months ago
1994
Dynamic synchronous Transfer Mode (DTM) is a new protocol suite based on synchronous fast circuit switching. The DTM network is based on bandwidth reservation and supports dynamic...
VLSISP
2002
14 years 11 months ago
2002
3:2 counters and 4:2 compressors have been widely used for multiplier implementations. In this paper, a fast 5:3 compressor is derived for high-speed multiplier implementations. Th...