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ARC
2008
Springer
104views Hardware» more  ARC 2008»
14 years 11 months ago
PARO: Synthesis of Hardware Accelerators for Multi-Dimensional Dataflow-Intensive Applications
Abstract. In this paper, we present the PARO design tool for the automated hardware synthesis of massively parallel embedded architectures for given dataflow dominant applications....
Frank Hannig, Holger Ruckdeschel, Hritam Dutta, J&...
ICML
2006
IEEE
15 years 10 months ago
Learning to impersonate
Consider Alice, who is interacting with Bob. Alice and Bob have some shared secret which helps Alice identify Bob-impersonators. Now consider Eve, who knows Alice and Bob, but doe...
Moni Naor, Guy N. Rothblum
CCR
2004
157views more  CCR 2004»
14 years 9 months ago
Designing BGP-based outbound traffic engineering techniques for stub ASes
Today, most multi-connected autonomous systems (AS) need to control the flow of their interdomain traffic for both performance and economical reasons. This is usually done by manu...
Steve Uhlig, Olivier Bonaventure
CIDR
2003
164views Algorithms» more  CIDR 2003»
14 years 11 months ago
Capacity Bound-free Web Warehouse
Web cache technologies have been developed as an extension of CPU cache, by modifying LRU (Least Recently Used) algorithms. Actually in web cache systems, we can use disks and ter...
Yahiko Kambayashi, Kai Cheng
ASAP
2005
IEEE
121views Hardware» more  ASAP 2005»
15 years 3 months ago
Using TLM for Exploring Bus-based SoC Communication Architectures
As billion transistor System-on-chips (SoC) become commonplace and design complexity continues to increase, designers are faced with the daunting task of meeting escalating design...
Sudeep Pasricha, Mohamed Ben-Romdhane