69 search results - page 11 / 14 » Fast Estimation of Timing Yield Bounds for Process Variation... |
92
Voted
ISQED
2010
IEEE
15 years 1 months ago
2010
IEEE
Circuit design under process variation can be formulated mathematically as a robust optimization problem with a yield constraint. Existing methods force designers to either resort...
109
Voted
ICDE
2012
IEEE
13 years 2 months ago
2012
IEEE
—On a stream of two dimensional data items (x, y) where x is an item identifier, and y is a numerical attribute, a correlated aggregate query requires us to first apply a selec...
ICCAD
2002
IEEE
15 years 8 months ago
2002
IEEE
Embedded system programs tend to spend much time in small loops. Introducing a very small loop cache into the instruction memory hierarchy has thus been shown to substantially red...
85
Voted
PR
2007
14 years 11 months ago
2007
Tuning SVM hyperparameters is an important step in achieving a high-performance learning machine. It is usually done by minimizing an estimate of generalization error based on the...
88
Voted
VLSID
2006
IEEE
16 years 13 sec ago
2006
IEEE
SoC design methodologies are under constant revision due to adoption of fast shrinking process technologies at nanometer levels. Nanometer process geometries exhibit new complex d...