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142
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ISQED
2007
IEEE
15 years 10 months ago
2007
IEEE
Clock distribution is one of the key limiting factors in any high speed, sub-100nm VLSI design. Unwanted clock skews, caused by variation effects like manufacturing variations, po...
128
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ISQED
2007
IEEE
15 years 10 months ago
2007
IEEE
In this paper, we address the interconnect-driven floorplanning problem that integrates OPC-friendly bus assignment with floorplanning. Buses consist of a number of horizontal/v...
133
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ISVLSI
2007
IEEE
15 years 10 months ago
2007
IEEE
— Y -interconnects for VLSI chips are based on the use of global and semi-global wiring in only 0◦ , 60◦ , and 120◦ . Though X-interconnects are fast replacing the traditio...
143
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MOBIQUITOUS
2007
IEEE
15 years 10 months ago
2007
IEEE
—This paper discusses the design and implementation of an ultra low power embedded GPS receiver node for use in remote monitoring situations where battery life is of the utmost i...
143
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SASO
2007
IEEE
15 years 10 months ago
2007
IEEE
With the rapidly falling price of hardware, and increasingly available bandwidth, the storage technology is seeing a paradigm shift from centralized and managed mode to distribute...