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ICCD
2004
IEEE
103views Hardware» more  ICCD 2004»
16 years 1 months ago
A Fast Delay Analysis Algorithm for The Hybrid Structured Clock Network
This paper presents a novel approach to reducing the complexity of the transient linear circuit analysis for a hybrid structured clock network. Topology reduction is first used to...
Yi Zou, Yici Cai, Qiang Zhou, Xianlong Hong, Sheld...
ICCD
2001
IEEE
120views Hardware» more  ICCD 2001»
16 years 1 months ago
Architectural Enhancements for Fast Subword Permutations with Repetitions in Cryptographic Applications
We propose two new instructions, swperm and sieve, that can be used to efficiently complete an arbitrary bit-level permutation of an n-bit word with or without repetitions. Permut...
John Patrick McGregor, Ruby B. Lee
ICCD
2001
IEEE
103views Hardware» more  ICCD 2001»
16 years 1 months ago
Improved ZDN-arithmetic for Fast Modulo Multiplication
In 1987 Sedlak proposed a modulo multiplication algorithm which is suitable for smart card implementation due to it’s low latency time. It is based on ZDN (zwei_drittel_N) arith...
Hagen Ploog, Sebastian Flügel, Dirk Timmerman...
ICCAD
2007
IEEE
148views Hardware» more  ICCAD 2007»
16 years 1 months ago
Fast exact Toffoli network synthesis of reversible logic
— The research in the field of reversible logic is motivated by its application in low-power design, optical computing and quantum computing. Hence synthesis of reversible logic...
Robert Wille, Daniel Große