406 search results - page 58 / 82 » Fast Increment Registers |
DAC
2006
ACM
15 years 10 months ago
2006
ACM
We address the problem of estimating controller delay from high-level specifications during behavioral synthesis. Typically, the critical path of a synthesised behavioral design g...
VLSID
2005
IEEE
15 years 10 months ago
2005
IEEE
This paper presents a highly efficient processor design methodology based on the LISA 2.0 language. Typically the architecture design phase is dominated by an iterative processor ...
72
Voted
ICCD
2002
IEEE
15 years 6 months ago
2002
IEEE
Subword parallelism has succeeded in accelerating many multimedia applications. Subword permutation instructions have been proposed to efficiently rearrange subwords in or among r...
100
Voted
IMA
2009
Springer
15 years 4 months ago
2009
Springer
Cache timing attacks are a class of side-channel attacks that is applicable against certain software implementations. They have generated significant interest when demonstrated ag...
69
Voted
3DIM
2007
IEEE
15 years 3 months ago
2007
IEEE
We present fast and accurate segmentation algorithms of range images of urban scenes. The utilization of these algorithms is essential as a pre-processing step for a variety of ta...