Sciweavers

406 search results - page 61 / 82
» Fast Increment Registers
Sort
View
104
Voted
FPL
2006
Springer
96views Hardware» more  FPL 2006»
15 years 1 months ago
Reducing the Space Complexity of Pipelined Routing Using Modified Range Encoding
Interconnect delays are becoming an increasingly significant part of the critical path delay for circuits implemented in FPGAs. Pipelined interconnects have been proposed to addre...
Allan Carroll, Carl Ebeling
3DIM
2003
IEEE
15 years 1 months ago
A Range Image Refinement Technique for Multi-view 3D Model Reconstruction
This paper presents a range image refinement technique for generating accurate 3D computer models of real objects. Range images obtained from a stereo-vision system typically expe...
Soon-Yong Park, Murali Subbarao
CDES
2006
106views Hardware» more  CDES 2006»
14 years 11 months ago
Reducing Memory References for FFT Calculation
Fast Fourier Transform (FFT) is one of the most widely used algorithms in digital signal processing. It is used in many signal processing and communication applications. many of t...
Ayman Elnaggar, Mokhtar Aboelaze
ICCAD
2001
IEEE
201views Hardware» more  ICCAD 2001»
15 years 6 months ago
An Integrated Data Path Optimization for Low Power Based on Network Flow Method
Abstract: We propose an effective algorithm for power optimization in behavioral synthesis. In previous work, it has been shown that several hardware allocation/binding problems fo...
Chun-Gi Lyuh, Taewhan Kim, Chien-Liang Liu
CODES
2005
IEEE
15 years 3 months ago
Memory access optimizations in instruction-set simulators
Design of programmable processors and embedded applications requires instruction-set simulators for early exploration and validation of candidate architectures. Interpretive simul...
Mehrdad Reshadi, Prabhat Mishra