Sciweavers

43 search results - page 8 / 9
» Fast Inductance Extraction of Large VLSI Circuits
Sort
View
VLSID
2007
IEEE
92views VLSI» more  VLSID 2007»
14 years 6 months ago
Floorplanning in Modern FPGAs
State-of-the-art FPGA architectures have millions of gates in CLBs, Block RAMs, and Multiplier blocks which can host fairly large designs. While their physical design calls for oor...
Pritha Banerjee, Susmita Sur-Kolay, Arijit Bishnu
FCCM
2005
IEEE
139views VLSI» more  FCCM 2005»
13 years 12 months ago
A Study of the Scalability of On-Chip Routing for Just-in-Time FPGA Compilation
Just-in-time (JIT) compilation has been used in many applications to enable standard software binaries to execute on different underlying processor architectures. We previously in...
Roman L. Lysecky, Frank Vahid, Sheldon X.-D. Tan
VLSI
2010
Springer
13 years 1 months ago
A design workflow for dynamically reconfigurable multi-FPGA systems
Multi-FPGA systems (MFS's) represent a promising technology for various applications, such as the implementation of supercomputers and parallel and computational intensive emu...
Alessandro Panella, Marco D. Santambrogio, Frances...
GLVLSI
1998
IEEE
124views VLSI» more  GLVLSI 1998»
13 years 10 months ago
Non-Refreshing Analog Neural Storage Tailored for On-Chip Learning
In this research, we devised a new simple technique for statically holding analog weights, which does not require periodic refreshing. It further contains a mechanism to locally u...
Bassem A. Alhalabi, Qutaibah M. Malluhi, Rafic A. ...
DAC
2010
ACM
13 years 4 months ago
Tradeoff analysis and optimization of power delivery networks with on-chip voltage regulation
Integrating a large number of on-chip voltage regulators holds the promise of solving many power delivery challenges through strong local load regulation and facilitates systemlev...
Zhiyu Zeng, Xiaoji Ye, Zhuo Feng, Peng Li