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» Fast Integrated Tools for Circuit Design with FPGAs
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ASPDAC
2007
ACM
98views Hardware» more  ASPDAC 2007»
15 years 1 months ago
Fast Analytic Placement using Minimum Cost Flow
Many current integrated circuits designs, such as those released for the ISPD2005[14] placement contest, are extremely large and can contain a great deal of white space. These new...
Ameya R. Agnihotri, Patrick H. Madden
DAC
2005
ACM
14 years 11 months ago
Closing the power gap between ASIC and custom: an ASIC perspective
We investigate differences in power between application-specific integrated circuits (ASICs) and custom integrated circuits, with examples from 0.6um to 0.13um CMOS. A variety of ...
David G. Chinnery, Kurt Keutzer
ISPD
2009
ACM
79views Hardware» more  ISPD 2009»
15 years 4 months ago
A routing approach to reduce glitches in low power FPGAs
Glitches (spurious transitions) are common in electronic circuits. In this paper we present a novel approach to reduce dynamic power in FPGAs by reducing glitches during the routi...
Quang Dinh, Deming Chen, Martin D. F. Wong
FPL
2007
Springer
100views Hardware» more  FPL 2007»
15 years 4 months ago
Clock-Aware Placement for FPGAs
The programmable clock networks in FPGAs have a significant impact on overall power, area, and delay. Not only does the clock network itself dissipate a significant amount of powe...
Julien Lamoureux, Steven J. E. Wilton
DATE
2009
IEEE
135views Hardware» more  DATE 2009»
15 years 4 months ago
Heterogeneous coarse-grained processing elements: A template architecture for embedded processing acceleration
Reconfigurable Architectures are good candidates for application accelerators that cannot be set in stone at production time. FPGAs however, often suffer from the area and perfor...
Giovanni Ansaloni, Paolo Bonzini, Laura Pozzi