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JSA
2007
142views more  JSA 2007»
14 years 9 months ago
Efficient FPGA hardware development: A multi-language approach
This paper presents a multi-language framework to FPGA hardware development which aims to satisfy the dual requirement of high level hardware design and efficient hardware impleme...
Khaled Benkrid, Abdsamad Benkrid, S. Belkacemi
ISPD
2005
ACM
185views Hardware» more  ISPD 2005»
15 years 3 months ago
Dragon2005: large-scale mixed-size placement tool
In this paper, we develop a mixed-size placement tool, Dragon2005, to solve large scale placement problems effectively. A top-down hierarchical approach based on min-cut partition...
Taraneh Taghavi, Xiaojian Yang, Bo-Kyung Choi
ASAP
1997
IEEE
156views Hardware» more  ASAP 1997»
15 years 2 months ago
Design methodology for digital signal processing
Improvements in semiconductor integration density and the resulting problem of having to manage designs of increasing complexity is an old one, but still current. The new challeng...
Gerhard Fettweis
ICCD
2006
IEEE
117views Hardware» more  ICCD 2006»
15 years 6 months ago
System-Level Energy Modeling for Heterogeneous Reconfigurable Chip Multiprocessors
—Field-Programmable Gate Array (FPGA) technology is characterized by continuous improvements that provide new opportunities in system design. Multiprocessors-ona-Programmable-Chi...
Xiaofang Wang, Sotirios G. Ziavras
MAM
2006
95views more  MAM 2006»
14 years 9 months ago
Stochastic spatial routing for reconfigurable networks
FPGA placement and routing is time consuming, often serving as the major obstacle inhibiting a fast edit-compile-test loop in prototyping and development and the major obstacle pr...
André DeHon, Randy Huang, John Wawrzynek