85 search results - page 16 / 17 » Fast Out-Of-Order Processor Simulation Using Memoization |
ISCA
2003
IEEE
15 years 2 months ago
2003
IEEE
With power density and hence cooling costs rising exponentially, processor packaging can no longer be designed for the worst case, and there is an urgent need for runtime processo...
IPPS
2000
IEEE
15 years 1 months ago
2000
IEEE
Buffered coscheduling is a scheduling methodology for time-sharing communicating processes in parallel and distributed systems. The methodology has two primary features: communica...
68
Voted
ISCA
1999
IEEE
15 years 1 months ago
1999
IEEE
In response to the growing gap between memory access time and processor speed, DRAM manufacturers have created several new DRAM architectures. This paper presents a simulation-bas...
IEEEPACT
2003
IEEE
15 years 2 months ago
2003
IEEE
Recent research shows that the high occupancy of Coherence Controllers (CCs) is a major performance bottleneck in scalable shared-memory multiprocessors. In this paper, we propose...
ISCA
1994
IEEE
15 years 1 months ago
1994
IEEE
Today's commodity microprocessors require a low latency memory system to achieve high sustained performance. The conventional high-performance memory system provides fast dat...