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» Fast Simulation Techniques for Design Space Exploration
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HPCA
2008
IEEE
16 years 3 days ago
Performance and power optimization through data compression in Network-on-Chip architectures
The trend towards integrating multiple cores on the same die has accentuated the need for larger on-chip caches. Such large caches are constructed as a multitude of smaller cache ...
Reetuparna Das, Asit K. Mishra, Chrysostomos Nicop...
79
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OOPSLA
2009
Springer
15 years 6 months ago
Scalable nonblocking concurrent objects for mission critical code
The high degree of complexity and autonomy of future robotic space missions, such as Mars Science Laboratory (MSL), poses serious challenges in assuring their reliability and efï¬...
Damian Dechev, Bjarne Stroustrup
VLDB
2004
ACM
92views Database» more  VLDB 2004»
15 years 5 months ago
Write-Optimized B-Trees
Large writes are beneficial both on individual disks and on disk arrays, e.g., RAID-5. The presented design enables large writes of internal B-tree nodes and leaves. It supports b...
Goetz Graefe
CANPC
2000
Springer
15 years 4 months ago
Transparent Network Connectivity in Dynamic Cluster Environments
Improvements in microprocessor and networking performance have made networks of workstations a very attractive platform for high-end parallel and distributed computing. However, t...
Xiaodong Fu, Hua Wang, Vijay Karamcheti
DAC
2008
ACM
16 years 23 days ago
DeFer: deferred decision making enabled fixed-outline floorplanner
In this paper, we present DeFer -- a fast, high-quality and nonstochastic fixed-outline floorplanning algorithm. DeFer generates a non-slicing floorplan by compacting a slicing fl...
Jackey Z. Yan, Chris Chu