1054 search results - page 22 / 211 » Fast Simulation Techniques for Design Space Exploration |
123
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DATE
2009
IEEE
16 years 2 days ago
2009
IEEE
— MPSoC is evolving towards processor-pool (PP)-based architectures, which employ hierarchical on-chip network for inter- and intra-PP communication. Since the design space of PP...
144
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IISWC
2008
IEEE
15 years 11 months ago
2008
IEEE
As multiprocessors become mainstream, techniques to address efficient simulation of multi-threaded workloads are needed. Multi-threaded simulation presents a new challenge: non-d...
186
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DAC
2010
ACM
15 years 5 months ago
2010
ACM
Given the increasing complexity of multi-processor systems-onchip, a wide range of parameters must be tuned to find the best trade-offs in terms of the selected system figures of ...
162
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ASAP
2005
IEEE
15 years 11 months ago
2005
IEEE
As billion transistor System-on-chips (SoC) become commonplace and design complexity continues to increase, designers are faced with the daunting task of meeting escalating design...
188
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TCAD
2002
15 years 5 months ago
2002
Specialized clustered very large instruction word (VLIW) processors combined with effective compilation techniques enable aggressive exploitation of the high instruction-level para...