1054 search results - page 44 / 211 » Fast Simulation Techniques for Design Space Exploration |
ASPDAC
2001
ACM
15 years 1 months ago
2001
ACM
Our earlier work for fast evaluation of power consumption of general cores in a system-on-a-chip described techniques that involved isolating high-level instructions of a core, me...
80
Voted
SPIN
2009
Springer
15 years 4 months ago
2009
Springer
Existing techniques for approximate storage of visited states in a model checker are too special-purpose and too DRAM-intensive. Bitstate hashing, based on Bloom filters, is good ...
92
Voted
LCTRTS
2010
Springer
15 years 4 months ago
2010
Springer
With increasingly more complex Multi-Processor Systems on Chip (MPSoC) and shortening time-to- market projections, Transaction Level Modeling and Platform Aware Design are seen as...
DATE
2000
IEEE
15 years 2 months ago
2000
IEEE
We present a technique for fast estimation of the power consumed by the cache and bus sub-system of a parameterized system-on-a-chip design for a given application. The technique ...
ICCAD
1995
IEEE
15 years 1 months ago
1995
IEEE
This paper addresses the problem of speeding up functional (delayindependent)logic simulation for synchronousdigital systems. The problem needs very little new motivation – cycl...