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RSP
2003
IEEE
103views Control Systems» more  RSP 2003»
15 years 2 months ago
An Instruction Throughput Model of Superscalar Processors
With advances in semiconductor technology, processors are becoming larger and more complex. Future processor designers will face an enormous design space, and must evaluate more a...
Tarek M. Taha, D. Scott Wills
83
Voted
DATE
2005
IEEE
134views Hardware» more  DATE 2005»
15 years 3 months ago
Assertion-Based Design Exploration of DVS in Network Processor Architectures
With the scaling of technology and higher requirements on performance and functionality, power dissipation is becoming one of the major design considerations in the development of...
Jia Yu, Wei Wu, Xi Chen, Harry Hsieh, Jun Yang 000...
DAC
2006
ACM
15 years 10 months ago
Exploring trade-offs in buffer requirements and throughput constraints for synchronous dataflow graphs
Multimedia applications usually have throughput constraints. An implementation must meet these constraints, while it minimizes resource usage and energy consumption. The compute i...
Sander Stuijk, Marc Geilen, Twan Basten
WSC
2004
14 years 11 months ago
Parallel Discrete Event Simulation of Space Shuttle Operations
This paper describes the application of parallel simulation techniques to represent structured functional parallelism present within the Space Shuttle Operations Flow, utilizing t...
José A. Sepúlveda, Luis C. Rabelo, M...
66
Voted
WSC
2000
14 years 11 months ago
Variance reduction techniques for value-at-risk with heavy-tailed risk factors
The calculation of value-at-risk (VAR) for large portfolios of complex instruments is among the most demanding and widespread computational challenges facing the financial industr...
Paul Glasserman, Philip Heidelberger, Perwez Shaha...