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ITC
1992
IEEE
76views Hardware» more  ITC 1992»
15 years 1 months ago
A Small Test Generator for Large Designs
In this paper we report an automatic test pattern generator that can handle designs with one million gates or more on medium size workstations. Run times and success rates, i.e. t...
Sandip Kundu, Leendert M. Huisman, Indira Nair, Vi...
DSN
2006
IEEE
15 years 3 months ago
Designing dependable storage solutions for shared application environments
The costs of data loss and unavailability can be large, so businesses use many data protection techniques, such as remote mirroring, snapshots and backups, to guard against failur...
Shravan Gaonkar, Kimberly Keeton, Arif Merchant, W...
DATE
2008
IEEE
161views Hardware» more  DATE 2008»
15 years 4 months ago
Spatial Correlation Extraction via Random Field Simulation and Production Chip Performance Regression
Statistical timing analysis needs a priori knowledge of process variations. Lack of such a priori knowledge of process variations prevents accurate statistical timing analysis, fo...
Bao Liu
DATE
2003
IEEE
132views Hardware» more  DATE 2003»
15 years 3 months ago
Scheduling and Timing Analysis of HW/SW On-Chip Communication in MP SoC Design
On-chip communication design includes designing software (SW) parts (operating system, device drivers, interrupt service routines, etc.) as well as hardware (HW) parts (on-chip co...
Youngchul Cho, Ganghee Lee, Sungjoo Yoo, Kiyoung C...
CODES
2006
IEEE
15 years 3 months ago
A formal approach to robustness maximization of complex heterogeneous embedded systems
Embedded system optimization typically considers objectives such as cost, timing, buffer sizes and power consumption. Robustness criteria, i.e. sensitivity of the system to variat...
Arne Hamann, Razvan Racu, Rolf Ernst