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FPL
2003
Springer
100views Hardware» more  FPL 2003»
15 years 11 months ago
Two Approaches for a Single-Chip FPGA Implementation of an Encryptor/Decryptor AES Core
In this paper we present a single-chip FPGA full encryptor/decryptor core design of the AES algorithm. Our design performs all of them, encryption, decryption and key scheduling pr...
Nazar A. Saqib, Francisco Rodríguez-Henr&ia...
CRYPTO
2012
Springer
234views Cryptology» more  CRYPTO 2012»
13 years 8 months ago
Homomorphic Evaluation of the AES Circuit
We describe a working implementation of leveled homomorphic encryption (without bootstrapping) that can evaluate the AES-128 circuit in three different ways. One variant takes und...
Craig Gentry, Shai Halevi, Nigel P. Smart
CHES
2006
Springer
111views Cryptology» more  CHES 2006»
15 years 10 months ago
Cache-Collision Timing Attacks Against AES
This paper describes several novel timing attacks against the common table-driven software implementation of the AES cipher. We define a general attack strategy using a simplified ...
Joseph Bonneau, Ilya Mironov
176
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FPL
2004
Springer
143views Hardware» more  FPL 2004»
15 years 10 months ago
Exploring Area/Delay Tradeoffs in an AES FPGA Implementation
Abstract. Field-Programmable Gate Arrays (FPGAs) have lately become a popular target for implementing cryptographic block ciphers, as a well-designed FPGA solution can combine some...
Joseph Zambreno, David Nguyen, Alok N. Choudhary
ASAP
2005
IEEE
96views Hardware» more  ASAP 2005»
15 years 12 months ago
On-Chip Lookup Tables for Fast Symmetric-Key Encryption
On public communication networks such as the Internet, data confidentiality can be provided by symmetric-key ciphers. One of the most common operations used in symmetric-key ciphe...
A. Murat Fiskiran, Ruby B. Lee