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» Fast circuit simulation on graphics processing units
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ISCA
2003
IEEE
150views Hardware» more  ISCA 2003»
15 years 2 months ago
Cyclone: A Broadcast-Free Dynamic Instruction Scheduler with Selective Replay
To achieve high instruction throughput, instruction schedulers must be capable of producing high-quality schedules that maximize functional unit utilization while at the same time...
Dan Ernst, Andrew Hamel, Todd M. Austin
ASAP
2009
IEEE
182views Hardware» more  ASAP 2009»
15 years 6 months ago
NeMo: A Platform for Neural Modelling of Spiking Neurons Using GPUs
—Simulating spiking neural networks is of great interest to scientists wanting to model the functioning of the brain. However, large-scale models are expensive to simulate due to...
Andreas Fidjeland, Etienne B. Roesch, Murray Shana...
WSC
1998
14 years 11 months ago
Avoiding the Blues for Airline Travelers
The fast growth in airline passenger traffic combined with the slow growth in airport capacity worldwide is putting a severe strain on the capability of airlines to adapt their pr...
Jane L. Snowdon, Soad El-Taji, Mario Montevecchi, ...
ISCAS
2007
IEEE
173views Hardware» more  ISCAS 2007»
15 years 3 months ago
Critical Charge Characterization for Soft Error Rate Modeling in 90nm SRAM
— Due to continuous technology scaling, the reduction of nodal capacitances and the lowering of power supply voltages result in an ever decreasing minimal charge capable of upset...
Riaz Naseer, Younes Boulghassoul, Jeff Draper, San...
ICIP
2009
IEEE
15 years 10 months ago
Real Time Stereo Vision Using Exponential Step Cost Aggregation On Gpu
In this paper, we propose a local cost aggregation approach for real time stereo vision on a graphics processing unit (GPU). Recent research shows that local approaches based on c...