Sciweavers

169 search results - page 31 / 34
» Fast circuit simulation on graphics processing units
Sort
View
CODES
2004
IEEE
15 years 1 months ago
A novel deadlock avoidance algorithm and its hardware implementation
This paper proposes a novel Deadlock Avoidance Algorithm (DAA) and its hardware implementation, the Deadlock Avoidance Unit (DAU), as an Intellectual Property (IP) core that provi...
Jaehwan Lee, Vincent John Mooney III
PC
2010
177views Management» more  PC 2010»
14 years 8 months ago
Parallel graph component labelling with GPUs and CUDA
Graph component labelling, which is a subset of the general graph colouring problem, is a computationally expensive operation that is of importance in many applications and simula...
Kenneth A. Hawick, Arno Leist, Daniel P. Playne
RSP
2003
IEEE
176views Control Systems» more  RSP 2003»
15 years 2 months ago
Rapid Design and Analysis of Communication Systems Using the BEE Hardware Emulation Environment
This paper describes the early analysis and estimation features currently implemented in the Berkeley Emulation Engine (BEE) system. BEE is an integrated rapid prototyping and des...
Chen Chang, Kimmo Kuusilinna, Brian C. Richards, A...
FPGA
2010
ACM
294views FPGA» more  FPGA 2010»
15 years 2 months ago
Axel: a heterogeneous cluster with FPGAs and GPUs
This paper describes a heterogeneous computer cluster called Axel. Axel contains a collection of nodes; each node can include multiple types of accelerators such as FPGAs (Field P...
Kuen Hung Tsoi, Wayne Luk
IPPS
2010
IEEE
14 years 7 months ago
Large-scale multi-dimensional document clustering on GPU clusters
Document clustering plays an important role in data mining systems. Recently, a flocking-based document clustering algorithm has been proposed to solve the problem through simulat...
Yongpeng Zhang, Frank Mueller, Xiaohui Cui, Thomas...