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ISSS
2002
IEEE
151views Hardware» more  ISSS 2002»
15 years 6 months ago
Tuning of Loop Cache Architectures to Programs in Embedded System Design
Adding a small loop cache to a microprocessor has been shown to reduce average instruction fetch energy for various sets of embedded system applications. With the advent of core-b...
Frank Vahid, Susan Cotterell
100
Voted
IJCAI
1989
15 years 2 months ago
Utilization Filtering: A Method for Reducing the Inherent Harmfulness of Deductively Learned Knowledge
This paper highlights a phenomenon that causes deductively learned knowledge to be harmful when used for problem solving. The problem occurs when deductive problem solvers encount...
Shaul Markovitch, Paul D. Scott
ICCAD
2001
IEEE
272views Hardware» more  ICCAD 2001»
15 years 10 months ago
NetBench: A Benchmarking Suite for Network Processors
— In this study we introduce NetBench, a benchmarking suite for network processors. NetBench contains a total of 9 applications that are representative of commercial applications...
Gokhan Memik, William H. Mangione-Smith, Wendong H...
CAV
2001
Springer
119views Hardware» more  CAV 2001»
15 years 6 months ago
Certifying Model Checkers
Model Checking is an algorithmic technique to determine whether a temporal property holds of a program. For linear time properties, a model checker produces a counterexample comput...
Kedar S. Namjoshi
VLSISP
2008
173views more  VLSISP 2008»
15 years 1 months ago
Fast Bit Gather, Bit Scatter and Bit Permutation Instructions for Commodity Microprocessors
Advanced bit manipulation operations are not efficiently supported by commodity word-oriented microprocessors. Programming tricks are typically devised to shorten the long sequence...
Yedidya Hilewitz, Ruby B. Lee