179 search results - page 34 / 36 » Fast performance estimation of block codes |
80
Voted
GLVLSI
2007
IEEE
15 years 3 months ago
2007
IEEE
We propose an interconnect reorganization algorithm for reduction stages in parallel multipliers. It aims at minimizing power consumption for given static probabilities at the pri...
ICIP
1998
IEEE
15 years 1 months ago
1998
IEEE
The block-matching motion estimation algorithm using a translational motion model cannot provide acceptable image quality in low bit-rate coding. To improve coding performance, we ...
IEEEPACT
2007
IEEE
15 years 3 months ago
2007
IEEE
Multi-core processors naturally exploit thread-level parallelism (TLP). However, extracting instruction-level parallelism (ILP) from individual applications or threads is still a ...
TIT
2002
14 years 9 months ago
2002
This paper considers noncoherent communication over a frequency-nonselective channel in which the time-varying channel gain is unknown a priori, but is approximately constant over ...
ICCAD
2008
IEEE
15 years 6 months ago
2008
IEEE
The ability to integrate diverse components such as processor cores, memories, custom hardware blocks and complex network-on-chip (NoC) communication frameworks onto a single chip...