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ICCAD
1994
IEEE
115views Hardware» more  ICCAD 1994»
15 years 3 months ago
Fast transient power and noise estimation for VLSI circuits
Abstract - Today's digital design systems are running out of steam, when it comes to meeting the challenges presented by simultaneous switching, power consumption and reliabil...
Wolfgang T. Eisenmann, Helmut E. Graeb
DAC
2008
ACM
16 years 24 days ago
Transistor level gate modeling for accurate and fast timing, noise, and power analysis
Current source based cell models are becoming a necessity for accurate timing and noise analysis at 65nm and below. Voltage waveform shapes are increasingly more difficult to repr...
S. Raja, F. Varadi, Murat R. Becer, Joao Geada
DATE
2005
IEEE
121views Hardware» more  DATE 2005»
15 years 5 months ago
Reduction of CMOS Power Consumption and Signal Integrity Issues by Routing Optimization
— This paper suggests a methodology to decrease the power of a static CMOS standard cell design at layout level by focusing on switched capacitance. The term switched is the key:...
Paul Zuber, Armin Windschiegl, Raúl Medina ...
GRID
2006
Springer
14 years 11 months ago
YA: Fast and Scalable Discovery of Idle CPUs in a P2P network
Discovery of large amounts of idle CPUs in fully distributed and shared Grid systems is needed in relevant applications and is still a challenging problem. In this paper we present...
Javier Celaya, Unai Arronategui
ASPDAC
2007
ACM
121views Hardware» more  ASPDAC 2007»
15 years 3 months ago
Timing-Aware Decoupling Capacitance Allocation in Power Distribution Networks
Power supply noise increases the circuit delay, which may lead to performance failure of a design. Decoupling capacitance (decap) addition is effective in reducing the power suppl...
Sanjay Pant, David Blaauw