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ISCAS
2007
IEEE
173views Hardware» more  ISCAS 2007»
15 years 3 months ago
Critical Charge Characterization for Soft Error Rate Modeling in 90nm SRAM
— Due to continuous technology scaling, the reduction of nodal capacitances and the lowering of power supply voltages result in an ever decreasing minimal charge capable of upset...
Riaz Naseer, Younes Boulghassoul, Jeff Draper, San...
ISBI
2008
IEEE
15 years 10 months ago
Monte Carlo assessment of time-of-flight benefits on the LYSO-based discovery RX PET/CT scanner
Time-Of-Flight (TOF) positron emission tomography (PET) was studied and preliminarily developed in the 80s, but the lack of a scintillator able to deliver proper time resolution a...
Parham Geramifar, Mohammad Reza Ay, Mojtaba Shamsa...
MICRO
2009
IEEE
133views Hardware» more  MICRO 2009»
15 years 4 months ago
A tagless coherence directory
A key challenge in architecting a CMP with many cores is maintaining cache coherence in an efficient manner. Directory-based protocols avoid the bandwidth overhead of snoop-based ...
Jason Zebchuk, Vijayalakshmi Srinivasan, Moinuddin...
HPCA
2009
IEEE
15 years 10 months ago
A novel architecture of the 3D stacked MRAM L2 cache for CMPs
Magnetic Random Access Memory (MRAM) is considered to be a promising future memory technology due to its low leakage power, high density and fast read speed. The heterogeneous int...
Guangyu Sun, Xiangyu Dong, Yuan Xie, Jian Li, Yira...
ICCAD
2005
IEEE
147views Hardware» more  ICCAD 2005»
15 years 6 months ago
NoCEE: energy macro-model extraction methodology for network on chip routers
In this paper we present NoCEE, a fast and accurate method for extracting energy models for packet-switched Network on Chip (NoC) routers. Linear regression is used to model the r...
Jeremy Chan, Sri Parameswaran